////////////////////////////////////////////////////////////////////////////// 
//
//  dwc_e12mp_phy_x4_ns_macros.v
//
//  UP16-specific global macros which are deemed globally useful
//
//  Original Author: Chris Jones
//  Current Owner:   Chris Jones
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2007 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: sobaihi $
//    $File: //dwh/up16/main/dev/pma/include/dwc_e12mp_phy_x4_ns_macros.v $
//    $DateTime: 2015/12/10 07:12:22 $
//    $Revision: #27 $
//
////////////////////////////////////////////////////////////////////////////// 

`ifndef DWC_E12MP_X4NS_MACROS_V
 `define DWC_E12MP_X4NS_MACROS_V

 `include "dwc_e12mp_phy_x4_ns_jtag_id_code.v"

 // Scan chain macros (PMA x1,x2,x4)
 // (avoiding multiplication because SDB gives warning)
 `define DWC_E12MP_X4NS_PMA_X1_SCAN_CR         (`DWC_E12MP_X4NS_PMA_SCAN_CR_SUP+`DWC_E12MP_X4NS_PMA_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_PMA_X2_SCAN_CR         (`DWC_E12MP_X4NS_PMA_SCAN_CR_SUP+`DWC_E12MP_X4NS_PMA_SCAN_CR_LANE+`DWC_E12MP_X4NS_PMA_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_PMA_X4_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X2_SCAN_CR+`DWC_E12MP_X4NS_PMA_SCAN_CR_LANE+`DWC_E12MP_X4NS_PMA_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_PMA_X1_SCAN_REF_RANGE  (`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_SUP+`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_LANE)
 `define DWC_E12MP_X4NS_PMA_X2_SCAN_REF_RANGE  (`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_SUP+`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_LANE+`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_LANE)
 `define DWC_E12MP_X4NS_PMA_X4_SCAN_REF_RANGE  (`DWC_E12MP_X4NS_PMA_X2_SCAN_REF_RANGE+`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_LANE+`DWC_E12MP_X4NS_PMA_SCAN_REF_RANGE_LANE)

 // Encodings for LOS filter settings
 //
 `define DWC_E12MP_X4NS_RX_LOS_FILT_NONE  2'b00
 `define DWC_E12MP_X4NS_RX_LOS_FILT_PCIE1 2'b01
 `define DWC_E12MP_X4NS_RX_LOS_FILT_PCIE2 2'b10
 `define DWC_E12MP_X4NS_RX_LOS_FILT_XAUI  2'b11

 // Timescale for UP16 modules requires 1ns units with sufficient precision for
 // modeling of timing recovery
 //
 `define DWC_E12MP_X4NS_TIMESCALE 1ns / 10fs

 `define DWC_E12MP_X4NS_PHSEL_LEN 8
 
 `define DWC_E12MP_X4NS_CYC_TIME 5 
  
 // Power states
 `define PSTATE_P0  2'b00
 `define PSTATE_P0S 2'b01
 `define PSTATE_P1  2'b10
 `define PSTATE_P2  2'b11
  
 // Data widths
 `define DATA_WIDTH_8B  2'b00
 `define DATA_WIDTH_10B 2'b01
 `define DATA_WIDTH_16B 2'b10
 `define DATA_WIDTH_20B 2'b11

 // DAC CTRL Bus Addresses
  // 0 - none
 `define DAC_CTRL_SEL_ATT_IDAC          5'd1
 `define DAC_CTRL_SEL_EQ_IDAC           5'd2
 `define DAC_CTRL_SEL_VGA1_IDAC         5'd3
 `define DAC_CTRL_SEL_DFE_SUME_IDAC     5'd4
 `define DAC_CTRL_SEL_DFE_SUMO_IDAC     5'd5
 `define DAC_CTRL_SEL_DFE_T2_IDAC       5'd6
 `define DAC_CTRL_SEL_DFE_T3_IDAC       5'd7
 `define DAC_CTRL_SEL_DFE_T4_IDAC       5'd8
 `define DAC_CTRL_SEL_DFE_T5_IDAC       5'd9
  // 10-15 not used 
 `define DAC_CTRL_SEL_DFE_T1EH_VDAC     5'd16
 `define DAC_CTRL_SEL_DFE_T1EL_VDAC     5'd17
 `define DAC_CTRL_SEL_DFE_T1OH_VDAC     5'd18
 `define DAC_CTRL_SEL_DFE_T1OL_VDAC     5'd19
 `define DAC_CTRL_SEL_DFE_T1EP_VDAC     5'd20 // even phase (for 2 phase slicer designs)
 `define DAC_CTRL_SEL_EDFE_T1EP_VDAC    5'd20 // even phase "P" (for 4 phase slicer designs)
 `define DAC_CTRL_SEL_DFE_T1OP_VDAC     5'd21 // odd phase (for 2 phase slicer designs)
 `define DAC_CTRL_SEL_EDFE_T1OP_VDAC    5'd21 // odd phase "P" (for 4 phase slicer designs)
 `define DAC_CTRL_SEL_DFE_ERR_EVEN_VDAC 5'd22
 `define DAC_CTRL_SEL_EDFE_T1EZ_VDAC    5'd23 // even phase "Zero" (for 4 phase slicer designs)
 `define DAC_CTRL_SEL_DFE_ERR_ODD_VDAC  5'd24
 `define DAC_CTRL_SEL_EDFE_T1OZ_VDAC    5'd25 // odd phase "Zero" (for 4 phase slicer designs)
 `define DAC_CTRL_SEL_SCOPE_MAX_VDAC    5'd26
  // 27 not used
 `define DAC_CTRL_SEL_SCOPE_MID_VDAC    5'd28
  // 29 not used
 `define DAC_CTRL_SEL_SCOPE_MIN_VDAC    5'd30
  // 31not used

 //FAST SUP (MPLL and Rtune)
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_MPLL_PWRUP_INIT_VAL 1'b1
 `define FAST_MPLL_LOCK_INIT_VAL  1'b1
 `elsif FAST_SUP
 `define FAST_MPLL_PWRUP_INIT_VAL 1'b1
 `define FAST_MPLL_LOCK_INIT_VAL  1'b1
 `else
 // synopsys translate_on
 `define FAST_MPLL_PWRUP_INIT_VAL 1'b0
 `define FAST_MPLL_LOCK_INIT_VAL  1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST TX Common Mode Charge-up
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_TX_VCM_HOLD_INIT_VAL 1'b1
 `elsif FAST_TX_VCM_HOLD
 `define FAST_TX_VCM_HOLD_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_TX_VCM_HOLD_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //Fast TX RX Detect
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_TX_RXDET_INIT_VAL 1'b1
 `elsif FAST_TX_RXDET
 `define FAST_TX_RXDET_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_TX_RXDET_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX Power-up (LOS and VREG/AFE)
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_VREG_EN_INIT_VAL    1'b1
 `define FAST_RX_CLK_DCC_EN_INIT_VAL 1'b1
 `elsif FAST_RX_PWRUP
 `define FAST_RX_VREG_EN_INIT_VAL    1'b1
 `define FAST_RX_CLK_DCC_EN_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_VREG_EN_INIT_VAL    1'b0
 `define FAST_RX_CLK_DCC_EN_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // Fast RX VCO wait times
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_VCO_WAIT_INIT_VAL 1'b1
 `elsif FAST_RX_VCO_WAIT
 `define FAST_RX_VCO_WAIT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_VCO_WAIT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // Fast RX VCO calibration
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_VCO_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_VCO_CAL
 `define FAST_RX_VCO_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_VCO_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST SIM CTRL FOR RX ADAPT CTRL
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_AFE_DFE_SETTLE_INIT_VAL 1'b1
 `elsif FAST_AFE_DFE_SETTLE
 `define FAST_AFE_DFE_SETTLE_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_AFE_DFE_SETTLE_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on
 
 `ifdef DWC_E12MP_X4NS_PMA_MPLL_ANA_BW
 `define DWC_E12MP_X4NS_MPLL_BW_WIDTH 11           //Width of mpll_bandwidth bus
 `else
 `define DWC_E12MP_X4NS_MPLL_BW_WIDTH 7            //Width of mpll_bandwidth bus
 `endif
 
 `define DWC_E12MP_X4NS_MPLL_BW_RANGE `DWC_E12MP_X4NS_MPLL_BW_WIDTH-1:0         //Width of mpll_bandwidth bus
 
 //Rx LOS oscillator frequency range
 `define RX_LOS_OSC_FREQ_MIN 249.0e6 //unit: Hz
 `define RX_LOS_OSC_FREQ_MAX 491.0e6 //unit: Hz

 //Rx LOS oscillator turn-on time range
 `define RX_LOS_OSC_TURNON_TIME_MIN 5.4 //unit: ns
 `define RX_LOS_OSC_TURNON_TIME_MAX 14.0 //unit: ns

 //Rx LOS oscillator turn-off time range
 `define RX_LOS_OSC_TURNOFF_TIME_MIN 0.1 //unit: ns
 `define RX_LOS_OSC_TURNOFF_TIME_MAX 0.1 //unit: ns

 //BURNIN oscillator frequency range
 `define BURNIN_OSC_FREQ_MIN 153.0e6 //unit: Hz
 `define BURNIN_OSC_FREQ_MAX 239.5e6 //unit: Hz

 //BURNIN oscillator turn-on time range
 `define BURNIN_OSC_TURNON_TIME_MIN 1.0 //unit: ns
 `define BURNIN_OSC_TURNON_TIME_MAX 1.0 //unit: ns

 //BURNIN oscillator turn-off time range
 `define BURNIN_OSC_TURNOFF_TIME_MIN 0.1 //unit: ns
 `define BURNIN_OSC_TURNOFF_TIME_MAX 0.1 //unit: ns

 //BEACON oscillator frequency range
 `define BEACON_OSC_FREQ_MIN 160.0e6 //unit: Hz
 `define BEACON_OSC_FREQ_MAX 400.0e6 //unit: Hz

 //BEACON oscillator turn-on time range
 `define BEACON_OSC_TURNON_TIME_MIN 1.0 //unit: ns
 `define BEACON_OSC_TURNON_TIME_MAX 1.0 //unit: ns

 //BEACON oscillator turn-off time range
 `define BEACON_OSC_TURNOFF_TIME_MIN 0.1 //unit: ns
 `define BEACON_OSC_TURNOFF_TIME_MAX 0.1 //unit: ns

 //TXDETECTRX strobe window timing
 `define TXDETECTRX_STROBE_WINDOW_START 3750.0 //unit: ns
 `define TXDETECTRX_STROBE_WINDOW_WIDTH 23050.0 //unit: ns

 `define TXDETECTRX_STROBE_WINDOW_START_SHORT 10.0 //unit: ns
 `define TXDETECTRX_STROBE_WINDOW_WIDTH_SHORT 10.0 //unit: ns

 //MPLL VCO parameters
 `define MPLL_VCO_PWRON_RUNT_TIME 1000      //unit: ns, Length of time to runt the clocks after VCO initial power on
 `define MPLL_VCO_PWRON_RUNT_TIME_SHORT 200 //unit: ns, Length of time to runt the clocks after VCO initial power on in short reset
 `define MPLL_VCO_RUNT_LOW_LIMIT 0.1        //unit: ns, MPLL VCO minimum runt pulse size
 `define MPLL_VCO_RUNT_HIGH_LIMIT 0.3       //unit: ns, MPLL VCO maximum runt pulse size
 `define MPLL_VCO_TUNE_RUNT_TIME 200        //unit: ns, Length of time to runt the clocks after coarse_tune changes
 `define MPLL_VCO_TUNE_STEP 0.0023          //Coarse tune step size -- factor of vco phase (defaults to 0.23%)
 `define MPLL_VCO_TUNE_WIDTH 8              //Width of coarse_tune bus

 //Rx CDR VCO parameters
 `define RX_VCO_PWRON_RUNT_TIME 1000      //unit: ns, Length of time to runt the clocks after VCO initial power on
 `define RX_VCO_PWRON_RUNT_TIME_SHORT 100 //unit: ns, Length of time to runt the clocks after VCO initial power on in short reset
 `define RX_VCO_RUNT_LOW_LIMIT 0.1        //unit: ns, Minimum runt pulse size
 `define RX_VCO_RUNT_HIGH_LIMIT 0.3       //unit: ns, Maximum runt pulse size

 `define RX_VCO_FREQ_TUNE_RUNT_TIME 200   //unit: ns, Length of time to runt the clocks after freq code changes
 `define RX_VCO_FREQ_TUNE_STEP 0.003      //Freq tune step size -- factor of vco phase (defaults to 0.3%)
 `define RX_VCO_FREQ_TUNE_WIDTH 10        //Width of freq tune word (freq_code)
 `define RX_VCO_INT_TUNE_STEP 0.000125    //Integration tune step size -- factor of vco phase (defaults to 0.0125%)
 `define RX_VCO_INT_TUNE_WIDTH 10         //Width of integration tune word (kint_lv)
 `define RX_VCO_PROP_TUNE_STEP 0.001      //Proportional tune step size -- factor of vco phase (defaults to 0.1%)
 `define RX_VCO_PROP_TUNE_WIDTH 3         //Width of proportional tune word (dn_lv/up_lv)

 `define PADS_PWRSW_TURNON_TIME  5000     //unit: ns, time for pads power switch to turn on
 `define PADS_PWRSW_TURNOFF_TIME 1000     //unit: ns, time for pads power switch to turn off

`endif
